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May 12, 2010
 
IDT Confidential
Low Limit Register
Low Limit Register
The Low Limit Register holds the lower limit for the nominal operating window. When the temperature drops below the Low Limit or rises up to meet
or exceed the Low Limit, then the EVENT
 pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register, then this
register becomes read-only.
TCRIT Limit Register
TCRIT Limit Register
The TCRIT Limit Register holds the TCRIT Limit. If the temperature exceeds the limit, the EVENT
 pin will be asserted. It will remain asserted until
the temperature drops below or equal to the limit minus hysteresis. If the TCRIT_LOCK bit is set as shown in the Configuration Register table, then
this register becomes read-only.
Temperature Data Register
Temperature Data Register
* Resolution defined based on value of TRES field of the Capabilities Register. Unused/unsupported bits will read as 0.
The Temperature Data Register holds the 10-bit + sign data for the internal temperature measurement as well as the status bits indicating which
error conditions, if any, are active. The encoding of bits B 12 through B0 is the same as for the temperature limit registers.
Bit 15  TCRIT; When set, the temperature is above the TCRIT Limit. This bit will remain set so long as the temperature is above TCRIT and will
automatically clear once the temperature has dropped below the limit minus the hysteresis.
Bit 14  HIGH; When set, the temperature is above the High Limit. This bit will remain set so long as the temperature is above the HIGH limit. Once
set, it will only be cleared when the temperature drops below or equal to the HIGH Limit minus the hysteresis.
Bit 13  LOW; When set, the temperature is below the Low Limit. This bit will remain set so long as the temperature is below the Low Limit minus
the hysteresis. Once set, it will only be cleared when the temperature meets or exceeds the Low Limit.
ADDR   R/W   B15/B7    B14/B6    B13/B5   B12/B4    B11/B3
B10/B2
B9/B1
B8/B0
Default
03
R/W



Sign
128
64
32
16
0000
8
4
2
1
0.5
0.25


ADDR   R/W   B15/B7    B14/B6    B13/B5   B12/B4    B11/B3
B10/B2
B9/B1
B8/B0
Default
04
R/W



Sign
128
64
32
16
0000
8
4
2
1
0.5
0.25


ADDR   R/W   B15/B7    B14/B6    B13/B5   B12/B4    B11/B3
B10/B2
B9/B1
B8/B0
Default
05
R
TCRIT
HIGH
LOW
Sign
128
64
32
16
N/A (0000)
8
4
2
1
0.5
0.25*
0.125*
0.0625*
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